Performance Evaluation of Approximate 4:2 Compressor in FinFET Technology

Abstract

This project uses FinFET technology to build and execute a 4:2 compressor that is both energy and space efficient. The main goal is to use FinFETs\' advantages over conventional CMOS circuits to improve the 4:2 compressor\'s performance. FinFETs are a great option for contemporary high-performance digital circuits because they provide better control over short-channel effects, lower leakage current, and faster switching. Using Cadence virtuoso software, the suggested design is simulated and verified with an emphasis on maximizing power consumption, energy efficiency, and area reduction. To get the intended performance metrics, the circuit design process entails careful selection of transistor sizes and optimization strategies. To demonstrate the advantages of the FinFET-based design. The circuit design process involves careful selection of transistor sizes, layout topologies, and optimization methodologies in order to achieve the desired performance metrics. A detailed analysis is conducted in order to illustrate the benefits of the FinFET-based design. The results demonstrate a significant gain in power and energy efficiency as well as a significant reduction in space when compared to conventional CMOS-based compressors.

Introduction

The increasing demand for energy-efficient digital circuits, particularly compressors used in DSP and machine learning accelerators, has led to the adoption of approximate computing and FinFET technology. A 4:2 compressor, which reduces four input bits into a sum and carry output, is critical for high-speed multipliers. Traditional exact designs ensure full accuracy but require complex gates and longer delays, while approximate designs trade some accuracy for reduced power, area, and delay.

This project proposes a FinFET-based approximate 4:2 compressor that leverages the superior switching speed, leakage control, and channel management of FinFETs. By simplifying the logic for Sum and Carry outputs, the design significantly lowers gate count, power consumption, and delay, making it suitable for error-tolerant applications such as image processing, signal processing, and neural network accelerators. Simulation using Cadence Virtuoso at the 20 nm node demonstrates that using 4-fin FinFETs optimizes drive strength and energy efficiency, achieving a lower power-delay product (PDP) compared to conventional CMOS compressors.

Conclusion

The device sizing was chosen with a gate length of 20 nm and a fin count of 4, yielding an effective width of 224 nm. The design was evaluated for delay, average power consumption, and power–delay product (PDP). From transient simulation results, the average propagation delay was found to be 2.55 ns, and the average power consumption was 25.32 nW, leading to a PDP of only 64.56 aJ. Compared to existing state-of-the-art compressor designs reported between 2015 and 2021, the proposed design demonstrates a significant reduction in power and PDP while maintaining a competitive delay performance. The extremely low PDP achieved in this design highlights the effectiveness of FinFET-based approximate computing in achieving energy-efficient arithmetic circuits. Since applications such as image processing, signal processing, and neural networks can tolerate minor computational errors, the proposed design provides an excellent trade-off between accuracy and efficiency. Therefore, it is well-suited for low-power, error-tolerant, and high-performance VLSI systems, making it a promising candidate for next-generation IoT and AI hardware.

References

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Copyright

Copyright © 2025 Mamindlapally Divyalatha, Vemula Sabitha. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.